Ad-hoc translations to close Verilog semantics gap

被引：0

作者：

Haufe, Christian ^{[1
]}

Rogin, Frank ^{[2
]}

机构：

[1] AMD Saxony LLC & Co KG, Dresden Design Ctr, Dresden, Germany

[2] Fraunhofer Inst Integrated Circuits, Div Design Automat, Dresden, Germany

来源：

2008 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, PROCEEDINGS | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes rules to transform Verilog HDL source code in order to propagate X-values on RTL models in a more realistic way, and to check for potential differences of RTL simulation results against expected silicon implementation behavior. By running X-propagation simulations in parallel to usual RTL simulation and debugging, RTL design bugs previously detected in gate-level simulations can be detected earlier now. A prototypical tool automatically implements the proposed transformation rules. Experimental results on two industrial hardware designs validate the usefulness of our approach and justify its application in everyday use.

引用

页码：195 / +

页数：2