Very Low Power Domino Logic Circuits Using Carbon Nanotube Field Effect Transistor Technology

As scaling of silicon transistors is reaching its extreme value, new technologies are developing to improve the performance of low power VLSI circuits. Carbon Nanotube Field Effect Transistor (CNTFET) emerges as an alternative to Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for designing low power circuits. In this paper, CNTFET technology is reviewed having very high carrier mobility and faster switching speed as compared to MOS devices. In CNTFET technology, one or more carbon nanotubes are used in place of a semiconductor channel that is used in MOSFET. It is observed that Carbon nanotube field effect transistors consumes very less power and have a very small delay as compared to Complementary Metal Oxide Semiconductor (CMOS). In this paper, different existing domino logic techniques are discussed and implemented using CNTFET technology. A new technique is proposed to reduce propagation delay, average power consumption and noise sensitivity of domino circuits. Domino OR gates with 2, 4, 8 and 16 inputs are implemented and simulated using the existing and proposed techniques. Simulation is done on H-Spice in PTM 32 nm BSIM 4.0 model at a clock frequency of 200 MHz in CNTFET technology. The proposed technique shows maximum power reduction of 70.99% and maximum delay reduction of 43.54% as compared to CMFD technique in CNTFET technology. The proposed technique shows maximum improvement of 1.4 times in Unity Noise Gain (UNG) as compared to CSK-DL technique for 16 input OR gate in CNTFET technology.