REAL-TIME EFFICIENT FPGA IMPLEMENTATION OF AES ALGORITHM

被引：0

作者：

El Maraghy, Mazen ^{[1
]}

Hesham, Salma ^{[1
]}

Abd El Ghany, Mohamed A. ^{[1
,2
]}

机构：

[1] German Univ, Elect & Commun Dept, Cairo, Egypt

[2] Tech Univ Darmstadt, Darmstadt, Germany

来源：

2013 IEEE 26TH INTERNATIONAL SOC CONFERENCE (SOCC) | 2013年

关键词：

AES; FPGA; VHDL; cryptography; hardware implementation; MicroBlaze;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An efficient optimized area and speed FPGA implementation for the Advanced Encryption Standard is proposed in this paper. The iterative looping method is adopted with multistage sub-pipelining architecture to achieve a 1.33 Gbps throughput for the AES-128 bit Encryption process. The proposed design operates at 425 MHz with 303 CLB slices on a Xilinx Virtex-5 XC5VLX50 FPGA Device. For real-time hardware evaluation, an end-user Java based application is developed. The software application is linked to the hardware design through the Xilinx MicroBlaze soft processor core.

引用

页码：203 / 208

页数：6

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