Floating Point FPGA Architecture of PID Controller

被引:0
作者
Wadgaonkar, Jagannath [1 ]
Bhole, Kalyani [1 ]
Singh, Prateek [1 ]
机构
[1] Coll Engn, Dept Instrumentat & Control, Pune 411005, Maharashtra, India
来源
2015 INTERNATIONAL CONFERENCE ON INDUSTRIAL INSTRUMENTATION AND CONTROL (ICIC) | 2015年
关键词
FPGA; HDL verilog; Matlab; system generator; IEEE; 754; IMPLEMENTATION; DESIGN; METHODOLOGY;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Proportional Integral Derivative (PID) Controller is most well-known and consistent with industry. It is applied to many applications such as flow, temperature, motor control, robotic applications, biomedical applications, etc. Many applications demands fast response. Parallel implementation of proportional, integral, derivative action accelerates its response which can be achieved by using field programmable gate arrays (FPGA). Floating point implementation of PID gives more truthfulness. In this paper, a sincere effort has been made to design and implement the floating point parallel architecture of PID controller using SPARTAN 3E(XC3S-500e) FPGA.
引用
收藏
页码:1259 / 1263
页数:5
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