Current-mode algorithmic pipeline analog-to-digital converter

被引：0
|
作者：
Correia, AJ
Guilherme, JC
Franca, JE
机构：
来源：
APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96 | 1996年
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中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Current-mode integrated circuit design techniques offering full compatibility with mainstream digital CMOS technology, have been investigated for the realization of an 8-bit 1 MHz analog-to-digital converter. This is based on a modular 1-bit-per-stage pipeline architecture employing a compact algorithmic processing circuitry in each stage. The-prototype chip fabricated in a 1.2 mu m digital CMOS technology occupies 0.655 mm(2) of silicon area and dissipates 50 mW at 5 V supply.
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页码：401 / 404
页数：4
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