Memory characteristics of a self-assembled monolayer of Pt nanoparticles as a charge trapping layer

被引：17

作者：

Choi, Hyejung ^{[1
]}

Choi, Byung-Sang ^{[2
]}

Kim, Tae-Wook ^{[1
]}

Jung, Seung-Jae ^{[1
]}

Chang, Man ^{[1
]}

Lee, Takhee ^{[1
]}

Hwang, Hyunsang ^{[1
]}

机构：

[1] Gwangju Inst Sci & Technol, Dept Mat Sci & Engn, Kwangju 500712, South Korea

[2] Chosun Univ, Dept Adv Met & Mat Engn, Kwangju 501759, South Korea

来源：

NANOTECHNOLOGY | 2008年 / 19卷 / 30期

关键词：

D O I：

10.1088/0957-4484/19/30/305704

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

A self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. Pt NPs with a narrow size distribution (diameter similar to 4 nm) were synthesized via an alcohol reduction method. The monolayer of these Pt NPs was immobilized on a SiO(2) substrate using poly(4-vinylpyridine) (P4VP) as a surface modifier. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window of 5.8 V under +/- 7 V for program/erase voltage. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices.

引用

页数：5

共 21 条

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