A novel low power bus coding technique for nanometer technology

被引：0

作者：

Zhao, Xin ^{[1
]}

Tian, Xi ^{[1
]}

Yan, ShaoShi ^{[1
]}

Guan, Yongfeng ^{[1
]}

机构：

[1] Natl Univ Def Technol, Sch Elect Sci & Engn, Changsha 410073, Peoples R China

来源：

ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2007年

关键词：

inter-wire capacitance; bus coding; low power;

D O I：

10.1109/ICASIC.2007.4415817

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The power dissipation on data bus is becoming a significant contributor to total power dissipation of nanometer CMOS circuits. As technology scales, the inter-wire capacitance increases greatly. The power consumed on inter-wire capacitance exceeds. on the grounded capacitance. In this paper, a new low power data bus coding technology is introduced which considers the inter-wire capacitance sufficiently. This method can be achieved with less hardware and the power dissipation can be reduced by 32.1% for 32-bit bus.

引用

页码：1066 / 1069

页数：4

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