A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

被引：14
|
作者：
Kang, Myounggon [1 ,2 ,3 ]
Hahn, Wookghee [3 ]
Park, Il Han [3 ]
Song, Youngsun [3 ]
Lee, Hocheol [3 ]
Choi, Kihwan [3 ]
Lim, Youngho [3 ]
Joe, Sung-Min [1 ,2 ]
Chae, Dong Hyuk [1 ,2 ,3 ]
Shin, Hyungcheol [1 ,2 ]
机构：
[1] Seoul Natl Univ, ISRC, Seoul 151742, South Korea
[2] Seoul Natl Univ, Sch Elect Engn & Comp Sci, Seoul 151742, South Korea
[3] Samsung Elect Co Ltd, Flash Design Team, Memory Business, Hwasung 445701, Gyeonggi, South Korea
来源：
JAPANESE JOURNAL OF APPLIED PHYSICS | 2011年 / 50卷 / 10期
关键词：
INTERFERENCE;
D O I：
10.1143/JJAP.50.100204
中图分类号：
O59 [应用物理学];
学科分类号：
摘要：
This paper presents an analytic model for NAND flash array where channel coupling embodies. Channel coupling effect which is becoming a more serious issue in developing high-density flash memory devices should be effectively suppressed. By applying the coupling model to a 30-nm NAND flash product, the simulation showed a good agreement with the measurement results. Also, complex problems in scaled NAND flash memories could be accurately explained by circuit simulations. This evaluation will be useful in developing high-density multi-level cell (MLC) NAND flash technologies. (C) 2011 The Japan Society of Applied Physics
引用
收藏
页数：2
相关论文
共 50 条
  • [1] The Compact Modeling of Channel Potential in Sub-30-nm NAND Flash Cell String
    Kang, Myounggon
    Lee, Kyunghwan
    Chae, Dong Hyuk
    Park, Byung-Gook
    Shin, Hyungcheol
    IEEE ELECTRON DEVICE LETTERS, 2012, 33 (03) : 321 - 323
  • [2] An Accurate Compact Model Considering Direct-Channel Interference of Adjacent Cells in Sub-30-nm NAND Flash Technologies
    Kang, Myounggon
    Park, Il Han
    Chang, Ik Joon
    Lee, Kyunghwan
    Seo, Seongjun
    Park, Byung-Gook
    Shin, Hyungcheol
    IEEE ELECTRON DEVICE LETTERS, 2012, 33 (08) : 1114 - 1116
  • [3] Flash memory device with 'I' shape floating gate for sub-70 nm NAND flash memory
    Jung, Sang-Goo
    Lee, Jong-Ho
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2006, 45 (42-45): : L1200 - L1202
  • [4] Flash memory device with 'I' shape floating gate for sub-70 nm NAND flash memory
    Jung, Sang-Goo
    Lee, Jong-Ho
    Japanese Journal of Applied Physics, Part 2: Letters, 2006, 45 (42-45):
  • [5] Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)
    Takeuchi, Ken
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (04) : 1227 - 1234
  • [6] Optimal Cell Design for Enhancing Reliability Characteristics for sub 30 nm NAND Flash Memory
    Cho, Eun Suk
    Kim, Hyun Jung
    Kim, Byoung Taek
    Song, Jai Hyuk
    Song, Du Heon
    Choi, Jeong-Hyuk
    Suh, Kang-Deog
    Chung, Chilhee
    2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2010, : 611 - 614
  • [7] Cryogenic operation of sub-30 nm nMOSFETs:: impact of device architecture
    Bertrand, G
    Deleonibus, S
    Souil, D
    Previtali, B
    Caillat, C
    Guégan, G
    Sanquer, M
    Balestra, F
    JOURNAL DE PHYSIQUE IV, 2002, 12 (PR3): : 45 - 49
  • [8] Device Considerations of Planar NAND Flash Memory for Extending towards Sub-20nm Regime
    Park, Youngwoo
    Lee, Jaeduk
    2013 5TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW), 2013, : 1 - 4
  • [9] Channel coupling phenomenon as scaling barrier of NAND flash memory beyond 20nm node
    Lee, ChangHyun
    Hwang, Jiyeong
    Fayrushin, Albert
    Kim, Hyunjung
    Son, Byoungkeun
    Park, Youngwoo
    Jin, Gyoyoung
    Jung, Eunseung
    2013 5TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW), 2013, : 72 - 75
  • [10] Resistivity of sub-30 nm Copper Lines
    Roberts, Jeanette M.
    Kaushik, Ananth P.
    Clarke, James S.
    2015 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE AND 2015 IEEE MATERIALS FOR ADVANCED METALLIZATION CONFERENCE (IITC/MAM), 2015, : 341 - 343
12345