Design of Ultra-low-leakage Logic Gates and Flip-flops in High-performance FinFET Technology

Multi-gate CMOS devices promise to usher an era of transistors with good electrostatic integrity at the sub-22nm nodes, which makes it essential to rethink traditional approaches to designing low-leakage digital logic and sequential elements formerly used in high-performance planar single-gate technologies. In the current work, we explore the design space of symmetric (Symm-Phi(G)) and asymmetric gate workfunction (Asymm-Phi(G)) FinFET logic gates, latches, and flip-flops for optimal trade-offs in leakage vs. delay and temperature in a high-performance FinFET technology. We demonstrate, using mixed-mode Sentaurus technology computer-aided design (TCAD) device simulations, that Asymm-Phi(G) shorted-gate n/p-FinFETs, which use both workfunctions corresponding to typical high-performance n/p-FinFETs, yield over two orders of magnitude lower leakage without excessive degradation in on-state current, in comparison to Symm-Phi(G) shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independent-gate (IG) FinFETs for leakage reduction. Results for elementary logic gates like INV, NAND2, NOR2, XOR2, and XNOR2 using Asymm-Phi(G) SG-mode FinFETs indicate that they are more optimally located in the leakage-delay spectrum in comparison to the most versatile configurations possible by mixing corresponding Symm-Phi(G) SG- and IG-mode FinFETs. Latches and flip-flops, however, require an astute combination of Symm-Phi(G) and Asymm-Phi(G) FinFETs to optimize leakage, delay, and setup time simultaneously.