Low-power CMOS analog signal processing using spatial mapping

This paper presents a low-power analog circuit for signal processing on pulse coded signals using spatial mapping. By successively delaying a periodic pulse train, and correlating delayed copies of the input signal with the input signal itself, the frequency component(s) are mapped spatially to output signals. The single delay line structure is then extended to a parallel structure with redundancy. In this way, we improve the signal-to-noise ratio. The design has been simulated and fabricated, and both simulation measurement results are presented, indicating the feasibility of the proposed methods.