A study of low jitter Phase Locked Loop for SPDIF

被引：0

作者：

Kim, JiHoon ^{[1
]}

Moon, Yong ^{[1
]}

机构：

[1] Soongsil Univ, Sch Elect Engn, Seoul, South Korea

来源：

PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017) | 2017年

关键词：

CMOS; CDR; SPDIF; PLL;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

CDR (Clock data recovery) circuit is an essential component for serial data communication. S/PDIF generates a lot of jitter from 2T and 3T. The PLL recognizes that the frequency changes in 2T and 3T portion. Change in frequency loses locking of the block. 3T detector reset Circuit is designed for reducing the jitter. Output jitter specifications of 9 frequencies are satisfied. 65nm CMOS process is used in this study.

引用

页码：184 / 185

页数：2

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