Critical length and resistance saturation effects in Al(Cu) interconnects

被引：5

作者：

Gall, M ^{[1
]}

Müller, J ^{[1
]}

Jawarani, D ^{[1
]}

Capasso, C ^{[1
]}

Hernandez, R ^{[1
]}

Kawasaki, I ^{[1
]}

机构：

[1] Motorola Inc, Adv Prod Res & Dev Lab, Austin, TX 78721 USA

来源：

MATERIALS RELIABILITY IN MICROELECTRONICS VIII | 1998年 / 516卷

关键词：

D O I：

10.1557/PROC-516-231

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new test structure for electromigration failure analysis of via-interconnect metallization schemes was developed. Multi-via/interconnect chain arrays were used in a parallel/serial testing arrangement. Due to improved statistical sampling, the multi-via test structures enabled measurement of drift velocity phenomena at via/interconnect interfaces with a very limited number of test devices per stressing condition, and without reducing the signal to noise ratio. Furthermore, realistic, production-type metallization schemes can be characterized without usually required "traditional" drift velocity-type metal stacks incorporating highly resistive shunt-layers. Critical length effects were investigated as a function of line length and current density. At interconnect lengths close to the critical Blech-length, resistance saturation effects were encountered and used for calculations of the critical current density length product, (jl)*. Furthermore, a new resistance saturation model was developed and found to correlate well with the acquired data. Critical length effects can accurately be measured and used for length-dependent interconnect performance evaluation on the device-level.

引用

页码：231 / 236

页数：6