Staircase charge-pumping study of trapping centers at grain-boundary in polysilicon thin film transistors

Polysilicon thin-film transistor (poly-Si TFT) characteristics are evaluated using the staircase charge-pumping (SCP) technique. By measuring the SCP current for various step times, we can obtain the trap state energy distributions at grain-boundaries for different (electron or hole emission) time constant windows. It is confirmed with the SCP technique that a large number of trap states (D-gb greater than or equal to 2x10(11) eV(-1). cm(-2)) exist at the grain-boundary region. As compared to those of n-channel TFT's, the trap states of p-channel TFT's are distributed over the broader time constant range up to 2 ms.