A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-/-μm CMOS

被引：21

作者：

Gaggl, R ^{[1
]}

Wiesbauer, A ^{[1
]}

Fritz, G ^{[1
]}

Schranz, C ^{[1
]}

Pessl, P ^{[1
]}

机构：

[1] Infineon Technol, A-9500 Villach, Austria

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 07期

关键词：

analog-to-digital converter (ADC); asymmetrical digital subscriber line (ADSL); delta-sigma modulator; dynamic biasing;

D O I：

10.1109/JSSC.2003.813216

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-resolution multibit sigma-delta analog-to-digital converter (ADC) implemented in a 0.18-mum CMOS technology is introduced. The circuit is targeted for an asymmetrical digital subscriber line (ADSL) central-office (CO) application [3]. An area- and power-efficient realization of a second-order single-loop 3-bit modulator with an oversampling ratio of 96 is presented. The SigmaDelta modulator features an 85-dB dynamic range over a 300-kHz signal bandwidth. The measured power consumption of the ADC core is only 15 mW. An innovative biasing circuitry is introduced for the switched-capacitor integrators.

引用

页码：1105 / 1114

页数：10

共 20 条

[1] A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter [J].