Fabrication of cylindrical nanopores and nanopore arrays in silicon-on-insulator substrates

被引：17

作者：

Petrossian, Leo ^{[1
]}

Wilk, Seth J. ^{[1
]}

Joshi, Punarvasu ^{[1
]}

Hihath, Sahar ^{[1
]}

Goodnick, Stephen M. ^{[1
]}

Thornton, Trevor J. ^{[1
]}

机构：

[1] Arizona State Univ, Dept Elect Engn, Ctr Solid State Elect Res, Arizona Inst Nanoelect, Tempe, AZ 85287 USA

来源：

JOURNAL OF MICROELECTROMECHANICAL SYSTEMS | 2007年 / 16卷 / 06期

基金：

美国国家科学基金会;

关键词：

coulter counting; ion channel; nanopore; nanoporous array; patch clamp; silicon-on-insulator (SOI);

D O I：

10.1109/JMEMS.2007.908435

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Electron-beam lithography and reactive ion etching were used to process silicon-on-insulator substrates for the fabrication of single cylindrical high-aspect-ratio solid-state nanopores and high-packing-density nanopore arrays. Minimum pore diameters of 40 nm were readily achieved with a high yield. The electrolyte concentration dependence of ion transport through single nanopores was measured for pores with diameters ranging from 40 to 140 nm. Measured single-nanopore conductances in high salt concentrations were compared to a simple model using a cylindrical resistance path and bulk solution conductivity. Electrochemical impedance spectroscopy was used to study the ac response of the device.

引用

页码：1419 / 1428

页数：10

共 46 条

[1] Membrane on a chip:: A functional tethered lipid bilayer membrane on silicon oxide surfaces [J].