Bayesian Optimization for High-Speed Channel Equalization

被引:2
|
作者
Kiguradze, Zurab [1 ]
Dikhaminjia, Nana [2 ]
Tsiklauri, Mikheil [1 ]
He, Jiayi [1 ]
Mutnury, Bhyrav [3 ]
Chada, Arun [3 ]
Drewniak, James [1 ]
机构
[1] Missouri S&T, Dept Elect & Comp Engn, Electromagnet Compatibil Lab, Rolla, MO 65409 USA
[2] Ilia State Univ, Dept Nat Sci & Engn, 3-5 Kakutsa Cholokashvili Ave, GE-0162 Tbilisi, Georgia
[3] Dell, Enterprise Prod Grp, One Dell Way,MS RR5-31, Round Rocks, TX 78682 USA
基金
美国国家科学基金会;
关键词
Equalization; DFE; FFE; Tap coefficients; Channel Response; Joint optimization; Bayesian Optimization;
D O I
10.1109/edaps47854.2019.9011654
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Equalization methods are used to recover the signal attenuated by channel loss. Different optimization algorithms are applied to find the best tap coefficients for each equalization that will improve eye opening and reduce bit error rate. The goal function for most equalization optimization algorithms is to reduce the difference between input and output signals, which is a linear optimization problem and can be solved relatively easily. This indirectly will increase eye height and improve eye diagram. Directly optimizing eye height is a non-linear problem and cannot be solved with analytical method. We are proposing FFE and DFE combined equalization optimization algorithm that optimizes directly eye height using Bayesian Optimization (BO). The proposed algorithm can be generalized for multi-level signals.
引用
收藏
页数:3
相关论文
共 50 条
  • [41] High-speed conveyor parameters optimization
    Hevko, B.M.
    Lyashuk, L.O.
    Rohatynska, L.R.
    Tarasyuk, Y.M.
    INMATEH - Agricultural Engineering, 2014, 43 (02): : 103 - 110
  • [42] Inverse optimization in high-speed networks
    Faragó, A
    Szentesi, A
    Szviatovszki, B
    DISCRETE APPLIED MATHEMATICS, 2003, 129 (01) : 83 - 98
  • [43] OPTIMIZATION OF TRANSPORT PROTOCOLS FOR HIGH-SPEED
    WAHL, T
    SALMONY, M
    IFIP TRANSACTIONS C-COMMUNICATION SYSTEMS, 1992, 6 : 405 - 419
  • [44] OPTIMIZATION OF HIGH-SPEED DIGITAL CIRCUITS
    ESHRAGHIAN, K
    MICROPROCESSING AND MICROPROGRAMMING, 1991, 32 (1-5): : 59 - 60
  • [45] Bayesian Equalization for LDPC Channel Decoding
    Salamanca, Luis
    Jose Murillo-Fuentes, Juan
    Perez-Cruz, Fernando
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2012, 60 (05) : 2672 - 2676
  • [46] Fast and Precise High-Speed Channel Modeling and Optimization Technique Based on Machine Learning
    Kim, Heegon
    Sui, Chunchun
    Cai, Kevin
    Sen, Bidyut
    Fan, Jun
    IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2018, 60 (06) : 2049 - 2052
  • [47] A Bayesian Framework for Optimizing Interconnects in High-Speed Channels
    Torun, Hakki M.
    Larbi, Mourad
    Swaminathan, Madhavan
    2018 IEEE MTT-S INTERNATIONAL CONFERENCE ON NUMERICAL ELECTROMAGNETIC AND MULTIPHYSICS MODELING AND OPTIMIZATION (NEMO), 2018,
  • [48] Design of high-speed channel switching system
    Hu, Yong
    Liu, Qian
    Wang, Quoxiong
    THIRD INTERNATIONAL CONFERENCE ON ELECTRONICS AND COMMUNICATION; NETWORK AND COMPUTER TECHNOLOGY (ECNCT 2021), 2022, 12167
  • [49] Maintaining channel compliance in high-speed backplanes
    Gavril, Bogdan
    EDN, 2006, 51 (21) : 91 - +
  • [50] HIGH-SPEED MULTI/CHANNEL COUNTING SYSTEM
    SPILLER, BHR
    BARTLEYD.GA
    INSTRUMENT PRACTICE, 1971, 25 (09): : 527 - &