A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous Time Feedforward Cascaded (CTFC) Op-Amps

被引：0

作者：

Chang, Kwuang-Han ^{[1
]}

Hsieh, Chih-Cheng ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Dept Elect & Elect Engn, Hsinchu, Taiwan

来源：

2018 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC): PROCEEDINGS OF TECHNICAL PAPERS | 2018年

关键词：

SAR ADC; high-resolution; calibration-free; full-analog; continuous-time; feedforward cascaded; stability;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A calibration-free 13-bit 10-MS/s full-analog SAR ADC integrates the functions of comparator, SAR logic, and DAC switches into multiple inverter-based regenerative amplifiers (IRAs) to have a double timing budget for settling and relax the bandwidth requirement of analog circuits compared to the conventional SAR ADC. The continuous-time feedforward cascaded (CTFC) Op-amps are proposed to enhance the residue SNR using open-loop low gain-bandwidth amplifiers instead of closed-loop high-precision amplifiers. The prototype in 40nm CMOS occupies 0.013 mm(2) and achieves 67.6 dB SNDR, 77.2 dB SFDR, 3.2 fJ/conv.-step FoM(w), and 176.6 dB FoMs without any calibration.

引用

页码：249 / 252

页数：4