A NEW HARDWARE FRIENDLY 2D-DCT HEVC COMPLIANT ALGORITHM AND ITS HIGH THROUGHPUT AND LOW POWER HARDWARE DESIGN

被引：0

作者：

Braatz, Luciano Almeida ^{[1
]}

Schneider Beck, Antonio Carlos ^{[2
]}

Zatt, Bruno ^{[1
]}

Agostini, Luciano Volcan ^{[1
]}

Palomino, Daniel Munari ^{[1
]}

Porto, Marcelo Schiavon ^{[1
]}

机构：

[1] Fed Univ Pelotas UFPel, Grad Program Comp Sci PPGC, Video Technol Res Grp ViTech, Pelotas, RS, Brazil

[2] Fed Univ Rio Grande Sul UFRGS, Inst Informat INF, Porto Alegre, RS, Brazil

来源：

2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) | 2019年

关键词：

HEVC; video coding; direct transform; DCT; hardware-friendly algorithm; hardware architecture;

D O I：

10.1109/icecs46596.2019.8965063

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a hardware-friendly algorithm to maximize the throughput of the Discrete Cosine Transform (DCT) of the High Efficiency Video Coding (HEVC), together with its hardware design. The Fast DCT (FCT) algorithm is based on the Cooley-Tuckey algorithm for the Fast Fourier Transform (FFT) with pre- and post-processing required to maintain the compliance with the HEVC. The resulting algorithm allows high throughput while maintaining low power dissipation. The designed hardware was synthesized for a 45-nm Nangate technology and it reaches a throughput of 81.28GSamples per second when consuming 12.33mW. Such energy efficiency and throughput surpass all related works in the literature.

引用

页码：654 / 657

页数：4

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