Properties of III-V Nanowires: MOSFETs and TunnelFETs

被引：0
|
作者：
Wernersson, Lars-Erik [1 ]
机构：
[1] Lund Univ, Elect & Informat Technol, Box 118, S-22100 Lund, Sweden
来源：
2017 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2017) | 2017年
基金：
瑞典研究理事会;
关键词：
III-V nanowires; III-V MOSFETs; InAs; InAs//GaSb; TFETs;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes the properties and performance status of vertical III-V nanowire transistors. The development of key process modules has advanced the vertical fabrication technology and competitive device performance is reported for InAs MOSFETs and TunnelFETs. Besides the benefits in electrostatic control and the ease in integration on Si substrates, the vertical transistors offers a path towards 3D device integration as demonstrated by the stacked track-and-hold circuit where a capacitor is integrated on top of the vertical transistor for area reduction.
引用
收藏
页码：99 / 100
页数：2
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