Utilizing surplus timing for power reduction

被引:43
作者
Hamada, M [1 ]
Ootaguro, Y [1 ]
Kuroda, T [1 ]
机构
[1] Toshiba Corp, Syst LSI Res & Dev Ctr, Kawasaki, Kanagawa, Japan
来源
PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2001年
关键词
D O I
10.1109/CICC.2001.929730
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.
引用
收藏
页码:89 / 92
页数:4
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