High-performance ternary operators for scrambling

This paper presents two new ternary operators which can be used in different scrambling crypto algorithms. The employment of the proposed operators (ScramOp1 and ScramOp2) leads to reduction in the number of decoding steps, equivalent to only one operation per digit for the receiver side. These operators are presented for the first time in ternary logic. There are some other ternary operators such as SUM, which are specifically suitable for computer arithmetic but they lack desirable efficiency for cryptographic applications. The transistor level designs of the operators are simulated by using Synopsys HSPICE with 32 nm bulk-CMOS technology. Simulation results demonstrate that ScramOpl and ScramOp2 achieve significant saving in energy consumption (2.11% and 12.14%) in comparison with SUM. Additionally, ScramOp2 requires only 52 transistors while 58 and 60 transistors are needed to implement ScramOp1 and SUM, respectively.