Identification of Parameter Domain for the Design of High-Speed I/O Interface

被引:0
|
作者
Kim, Seungwon [1 ]
Kim, Youngmin [2 ]
Han, Ki Jin [1 ]
机构
[1] Ulsan Natl Inst Sci & Technol, Sch Elect & Comp Engn, Ulsan 44919, South Korea
[2] Kwangwoon Univ, Dept Comp Engn, Seoul 01897, South Korea
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
To construct design rules for high-speed I/O interfaces, a method to identify the domain of design parameters for given electrical specifications is proposed in this paper. Since the shape of parameter domain is arbitrary and difficult to describe accurately, we simplify the problem by considering cubic domains only. Each domain is tested whether it belongs to the original parameter domain by Monte-Carlo sampling, and the volume of the domain is maximized by an optimization algorithm. During the procedure, computational burden due to a large number of samplings is addressed by reusing previously sampled data. By applying the developed method to a typical memory I/O interface model, we show the proposed approach can provide a practical and quantitative guideline for high-speed channel design.
引用
收藏
页码:67 / 70
页数:4
相关论文
共 50 条
  • [31] Identification of key design parameters of high-speed train for optimal design
    Zhang, J.
    Ding, G. F.
    Zhou, Y. S.
    Jiang, J.
    Ying, X.
    Qin, S. F.
    INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY, 2014, 73 (1-4): : 251 - 265
  • [32] Resistor-Triggered SCR Device for ESD Protection in High-Speed I/O Interface Circuits
    Lin, Chun-Yu
    Chen, Chun-Yu
    IEEE ELECTRON DEVICE LETTERS, 2017, 38 (06) : 712 - 715
  • [33] High-speed design
    不详
    MICROWAVES & RF, 1998, 37 (13) : 173 - 173
  • [34] High-speed I/O tests in high-volume manufacturing
    Sheibani, Shida
    2006 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, 2006, : 1085 - +
  • [35] High-speed I/O tests in high-volume manufacturing
    Swing, Brian
    2006 IEEE International Test Conference, Vols 1 and 2, 2006, : 1087 - 1088
  • [36] Design of high-speed information channel for satellite test based on serial Rapid I/O
    Zhang Bo
    Liang Jun
    Liu Li
    Gao Qi
    Cui Xiuhai
    PROCEEDINGS OF 2019 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS (ICEMI), 2019, : 1500 - 1507
  • [37] Design and optimization of DTSCR for high-speed I/O ESD protection of on-chip ICs
    Liang, Hailian
    Yang, Yanni
    Sun, Jun
    Liu, Junliang
    Cao, Xiyue
    Gu, Xiaofeng
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2022, 37 (04)
  • [38] Design and Characterization of ESD Protection Devices for High-Speed I/O in Advanced SOI Technology
    Cao, Shuqing
    Salman, Akram A.
    Chun, Jung-Hoon
    Beebe, Stephen G.
    Pelella, Mario M.
    Dutton, Robert W.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (03) : 644 - 653
  • [39] Gateway to chips: High speed I/O signalling and interface
    Kumar, Nidhir
    Velu, Senthil N.
    Verma, Rajan
    21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 3 - 4
  • [40] Design Of High-speed Decoder For New High-Speed Bus
    Zhang Weigong
    Yang Bo
    Ding Rui
    Hu Yongqin
    INFORMATION TECHNOLOGY FOR MANUFACTURING SYSTEMS, PTS 1 AND 2, 2010, : 958 - 962