Stress-induced voiding in stacked tungsten via structure

被引:9
|
作者
Domae, S [1 ]
Masuda, H [1 ]
Tateiwa, K [1 ]
Kato, Y [1 ]
Fujimoto, M [1 ]
机构
[1] Matsushita Elect Corp, ULSI Proc Technol Dev Ctr, Minami Ku, Kyoto 601, Japan
来源
1998 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 36TH ANNUAL | 1998年
关键词
D O I
10.1109/RELPHY.1998.670663
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The stress-induced voiding (SV) in Al-alloy films with stacked tungsten via structures was investigated with using new test structures. Voids were found in interconnections with stacked and borderless vias that had resistance increase after aging tests. Failure occurs most frequently when the test structures are stored at around 250 degrees C. This behavior can be explained by the diffusion creep model just like SV in a flat line [1]. A model of SV was obtained with thermal stress simulation and transmission electron microscopy (TEM) observation. Stress increases between upper and lower plugs with temperature increase over 175 degrees C.. Grains, which have high-angle misorientation, are often found above plugs. The tensile stress and grain misorientation should accelerate the void growth. O-2 plasma post metal etch treatment was found to be effective to eliminate SV in stacked via structure.
引用
收藏
页码:318 / 323
页数:6
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