Cascoded Flipped Voltage Follower Based Output-Capacitorless Low-Dropout Regulator for SoCs
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作者:
Li, Guangxiang
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Sun Yat Sen Univ, Sch Phys & Engn, Guangzhou, Guangdong, Peoples R ChinaSun Yat Sen Univ, Sch Phys & Engn, Guangzhou, Guangdong, Peoples R China
Li, Guangxiang
[1
]
Guo, Jianping
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机构:
Sun Yat Sen Univ, Sch Phys & Engn, Guangzhou, Guangdong, Peoples R China
SYSU CMU Shunde Int Joint Res Inst, Foshan, Peoples R ChinaSun Yat Sen Univ, Sch Phys & Engn, Guangzhou, Guangdong, Peoples R China
Guo, Jianping
[1
,2
]
Zheng, Yanqi
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机构:
Sun Yat Sen Univ, Sch Phys & Engn, Guangzhou, Guangdong, Peoples R China
SYSU CMU Shunde Int Joint Res Inst, Foshan, Peoples R ChinaSun Yat Sen Univ, Sch Phys & Engn, Guangzhou, Guangdong, Peoples R China
Zheng, Yanqi
[1
,2
]
Huang, Mo
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机构:
Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau, Peoples R ChinaSun Yat Sen Univ, Sch Phys & Engn, Guangzhou, Guangdong, Peoples R China
Huang, Mo
[3
]
Chen, Dihu
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机构:
Sun Yat Sen Univ, Sch Phys & Engn, Guangzhou, Guangdong, Peoples R China
SYSU CMU Shunde Int Joint Res Inst, Foshan, Peoples R ChinaSun Yat Sen Univ, Sch Phys & Engn, Guangzhou, Guangdong, Peoples R China
Chen, Dihu
[1
,2
]
机构:
[1] Sun Yat Sen Univ, Sch Phys & Engn, Guangzhou, Guangdong, Peoples R China
[2] SYSU CMU Shunde Int Joint Res Inst, Foshan, Peoples R China
[3] Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau, Peoples R China
来源:
2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC)
|
2015年
A novel cascoded flipped voltage follower (CAFVF) based output-capacitorless low-dropout (LDO) regulator is proposed and implemented in 0.18-mu m CMOS technology. With a cascode current source (CCS) embedded into the CAFVF structure, the proposed LDO regulator achieves 58.6-dB DC gain in heavy loading condition (100 mA), which is 44-dB for the conventional CAFVF counterpart under identical conditions. The cascode compensation technique is introduced to widen the loop bandwidth and reduce the minimal loading requirement. With a 5-pF compensation capacitor, the minimum load current to keep the proposed LDO regulator stable is reduced to 50 mu A. In addition, the unity-gain frequency (UGF) is extended from 1.51 MHz to 2.36 MHz in 100-mA loading condition. Moreover, an accurate stability analysis without ignoring any channel resistance has been presented in this work. Simulation results show that the LDO regulator consumes an ultra-low quiescent current (I-q) of 14 mu A for input voltage ranging from 1.2 V to 1.8 V, with a dropout voltage (V-drop) of 200 mV.