Simplified logical modulator for the reduction of common mode voltage in alternating current drives

被引:0
作者
Kullan, Murugesan [1 ]
Mahadevan, Senthil Kumaran [1 ]
Johnson, Anitha Roseline [1 ]
机构
[1] Sri Sivasubramaniya Nadar Coll Engn, Dept Elect & Elect Engn, Chennai, Tamil Nadu, India
关键词
Common mode voltage; Dead time; MATLAB; SPWM; System generator; THD; BEARING CURRENTS; PWM ALGORITHM; INVERTER; ELIMINATION; SPIKES;
D O I
10.1007/s43236-021-00303-y
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes the reduction of common mode voltage (CMV) magnitude using a simplified logical modulator (SLM). This modulator uses the ideas of space vectors to detect and eliminate the high common mode vectors produced by carrier phase-shifted sine pulse width modulation generator. The proposed SLM has an inherent ability to eliminate the CMV spikes due to dead time, but it introduces short circuit vectors (SCVs). This issue is addressed by designing an SCV eliminator (SCVE). The performance of the SLM-SCVE is validated through simulations. The proposed SLM-SCVE is implemented using MATLAB-Xilinx system generator interface in Spartan 3E-FPGA and tested in a prototype hardware. The proposed SLM-SCVE proves to be a simple and reliable solution for the reduction of CMV in industrial application because finite number of logic gates is used.
引用
收藏
页码:1680 / 1689
页数:10
相关论文
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