Efficient Time-Domain In-Memory Computing Based on TST-MRAM

被引：9

作者：

Wang, Jinkai ^{[1
]}

Zhang, Yue ^{[1
,2
]}

Lian, Chenyu ^{[1
]}

Bai, Yining ^{[1
]}

Huang, Zhe ^{[1
]}

Wang, Guanda ^{[1
]}

Zhang, Kun ^{[1
]}

Zhang, Youguang ^{[1
]}

Zhao, Weisheng ^{[1
,2
]}

机构：

[1] Beihang Univ, Fert Beijing Inst, Sch Microelect, BDBC, Beijing 100191, Peoples R China

[2] Beihang Univ, Hefei Innovat Res Inst, Nanoelect Sci & Technol Ctr, Hefei 230013, Peoples R China

来源：

2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2020年

基金：

中国国家自然科学基金;

关键词：

In-memory computing; Time-domain; Toggle spin torque MRAM; Multi-digit addition; LOW-POWER; DESIGN; XNOR; XOR;

D O I：

10.1109/iscas45731.2020.9180658

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In-memory computing is highly promising to address the processor-memory data transfer bottleneck in current computational paradigm. We firstly propose a time-domain in-memory computing (TIMC) scheme based on highspeed low-power toggle spin torque random access memory (TST-MRAM). The difference of voltage drops of bitline caused by simultaneously-activated bit-cells is reflected to time domain. Reconfigurable logic operations can be performed by utilizing D flip-flops (DFFs) to record the outputs at different moments. In order to demonstrate the advantages of this scheme in terms of speed and energy consumption, an efficient multi-digit addition circuit has been designed and analyzed. Compared with existing IMC schemes, such as spin-transfer torque computing-in-memory (STT-CiM) structure, up to 67% energy saving and 10 times delay improvement can be achieved in the case of four-digit addition by using TIMC scheme.

引用

页数：5

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