Crosstalk noise verification in digital designs with interconnect process variations

被引：10

作者：

Nagaraj, NS ^{[1
]}

Balsara, P ^{[1
]}

Cantrell, C ^{[1
]}

机构：

[1] Texas Instruments Inc, Dallas, TX 75243 USA

来源：

VLSI DESIGN 2001: FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN | 2001年

关键词：

D O I：

10.1109/ICVD.2001.902686

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Interconnect parasitics are playing a significant role in design and analysis in deep sub-micron (DSM) technologies. Interconnect process variations could play a significant role in achieving predictable yield. Crosstalk noise is one of the increasingly important careabouts in DSM designs. In this paper, a practical method to analyze the crosstalk noise effects with interconnect process variations using corner-based approach is described. The results from application of this method on a large DSP design implemented in 0.18u technology is presented. Application of the proposed method resulted in detection of a new worstcase interconnect process corner that was not included in the design methodology.

引用

页码：365 / 370

页数：6

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