A Power-Predictive Environment for Fast and Power-Aware ASIC-Based FIR Filter Design

Nowadays, the amount of small devices performing any kind of Digital Signal Processing (DSP) has increased drastically. On the other hand, the limited energy available to such battery-powered devices is a real problem. In DSP applications, one of the most important operations is the Finite Impulse Response (FIR) filter computation. The main FIR filter characteristics are the linear phase and feed forward implementation, which make it very useful for building high stable performance filters. However, the minimal designed coefficients bit-width, in integer representation, varies for each design. The main goal of this paper is to present a power-predictive environment for fast and power-aware FIR filter design. The proposed approach searches a set of powerefficient FIR Filter during the mathematical design based on a proposed power-predictive function which is performed using both the number of taps and the bit-width of the filter. Synthesis results was performed using Cadence RTL Compiler synthesis tool for all the range of filter specifications to validate the proposed power-predictive function and the filter methodology. The main results show that the proposed power-predictive environment enables a fast and power-aware decision even in mathematical design level enabling saves in power dissipation with better filter quality, and also enabling a reduction in the time-to-market, which nowadays is a very important requirement.