Harvest rate of reconfigurable pipelines

被引:1
作者
Shi, WP
Chang, MF
Fuchs, WK
机构
[1] NATL CHIAO TUNG UNIV,DEPT COMP SCI & INFORMAT ENGN,HSINCHU,TAIWAN
[2] PURDUE UNIV,SCH ELECT & COMP ENGN,W LAFAYETTE,IN 47907
基金
美国国家科学基金会;
关键词
harvest rate; yield; reconfigurable arrays; defect tolerance; pipelines; random graphs; percolation;
D O I
10.1109/12.543713
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. In this paper, we give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: There are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the ''shifting'' reconfiguration as weighted chains in a partial ordered set, we prove when n = Theta(m), the harvest rate is between 34% and 72%.
引用
收藏
页码:1200 / 1203
页数:4
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