Improved analytical model of surface potential with modified boundary conditions for double gate tunnel FETs

被引：5

作者：

Lu, Bin ^{[1
]}

Lu, Hongliang ^{[1
]}

Zhang, Yuming ^{[1
]}

Zhang, Yimen ^{[1
]}

Cui, Xiaoran ^{[1
]}

Jin, Chengji ^{[1
]}

Liu, Chen ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Lab Wide Band Gap Semicond Mat & Devices China, Xian 710071, Shaanxi, Peoples R China

来源：

MICROELECTRONICS RELIABILITY | 2017年 / 79卷

关键词：

Analytical model; Boundary conditions; Surface potential; Tunnel field-effect transistor; FIELD-EFFECT TRANSISTOR; THRESHOLD VOLTAGE; MOSFETS; DESIGN; SI;

D O I：

10.1016/j.microrel.2017.05.013

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, an improved analytical model of the channel surface potential in the tunnel field effect transistors is established with modified boundary conditions considering the source and drain depletion widths, avoiding the deviation of the channel potential and the overestimate on the electric field. Based on the proposed surface potential model, the threshold voltage model is also developed with the transconductance change method. The influences of the channel and oxide structures on surface potential and threshold voltage are investigated. The good agreement is obtained by the comparison of the modeling results with the numerical simulation results, verifying the validation of the proposed model, and it also implied that this model will be helpful for the further investigation of TFETs. (C) 2017 Published by Elsevier Ltd.

引用

页码：231 / 238

页数：8

共 18 条

[1] A new definition of threshold voltage in Tunnel FETs
Boucart, Kathy
Ionescu, Adrian Mihai
[J]. SOLID-STATE ELECTRONICS, 2008, 52 (09) : 1318 - 1323
[2] Two-dimensional model of a heterojunction silicon-on-insulator tunnel field effect transistor
Chander, Sweta
Baishya, S.
[J]. SUPERLATTICES AND MICROSTRUCTURES, 2016, 90 : 176 - 183
[3] A Two-Dimensional Gate Threshold Voltage Model for a Heterojunction SOI-Tunnel FET With Oxide/Source Overlap
Chander, Sweta
Baishya, Srimanta
[J]. IEEE ELECTRON DEVICE LETTERS, 2015, 36 (07) : 714 - 716
[4] Strained Si and SiGe tunnel-FETs and complementary tunnel-FET inverters with minimum gate lengths of 50 nm
Knoll, L.
Richter, S.
Nichau, A.
Trellenkamp, S.
Schaefer, A.
Bourdelle, K. K.
Hartmann, J. M.
Zhao, Q. T.
Mantl, S.
[J]. SOLID-STATE ELECTRONICS, 2014, 97 : 76 - 81
[5] Li Y., 2015, INT J NUMER MODELL E
[6] Mori Y, 2016, 2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), P188, DOI 10.1109/SNW.2016.7578044
[7] Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications
Narang, Rakhi
Saxena, Manoj
Gupta, R. S.
Gupta, Mridula
[J]. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2012, 12 (04) : 482 - 491
[8] Threshold voltage extraction in Tunnel FETs
Ortiz-Conde, Adelmo
Garcia-Sanchez, Francisco J.
Muci, Juan
Sucre-Gonzalez, Andrea
Martino, Joao Antonio
Der Agopian, Paula Ghedini
Claeys, Cor
[J]. SOLID-STATE ELECTRONICS, 2014, 93 : 49 - 55
[9] Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits
Pal, Ashish
Sachid, Angada B.
Gossner, Harald
Rao, V. Ramgopal
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (04) : 1045 - 1053
[10] Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs
Prabhat, Vishwa
Dutta, Aloke K.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (05) : 2190 - 2196

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