Design of Low-Power High-Speed Divide-by-2/3 Prescalers with Improved True Single-Phase Clock Scheme

被引：0
|
作者：
Jia, Song [1 ]
Yan, Shilin [1 ]
Wang, Yuan [1 ]
Zhang, Ganggang [1 ]
机构：
[1] Peking Univ, Inst Microelect, Key Lab Microelect Devices & Circuits, Beijing, Peoples R China
来源：
2014 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC) | 2014年
关键词：
D-flip-flop (DFF); frequency divider; prescaler; true single-phase clocked (TSPC) logic;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
New design improvement aiming to reduce the power consumption of true single-phase clock-based dual modulus divide-by-2/3 prescalers is presented. The first latch stages of TSPC FFs are merged to reduce power and capacitance. Also, a pass transistor is introduced to cut off short circuit current. Hspice simulation of the proposed scheme in 40nm process demonstrates best power efficiency and power-delay product among referenced designs. Besides, it shows comparable speed with extended TSPC prescalers.
引用
收藏
页码：241 / 243
页数：3
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