Three hardware implementations for the binary modular exponentiation: Sequential, parallel and systolic

被引：1

作者：

Nedjah, N ^{[1
]}

Mourelle, LD ^{[1
]}

机构：

[1] Univ Estado Rio De Janeiro, Fac Engn, Dept Syst Engn & Computat, Rio De Janeiro, Brazil

来源：

15TH SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/CAHPC.2003.1250344

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Modular exponentiation is the cornerstone computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. This paper describes the characteristics of three architectures designed to implement modular exponentiation using the fast binary method: the first FPGA prototype has a sequential architecture, the second has a parallel architecture and the third has a systolic array-based architecture. The paper compares the three prototypes using the time x area classic factor. All three prototypes implement the modular multiplication using the popular Montgomery algorithm.

引用

页码：246 / 253

页数：8

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