Run-time reconfiguration: Towards reducing the density requirements of FPGAs

被引：0

作者：

Brunham, K ^{[1
]}

Kinsner, W ^{[1
]}

机构：

[1] Univ Manitoba, Dept Elect & Comp Engn, Winnipeg, MB R3T 5V6, Canada

来源：

CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING 2001, VOLS I AND II, CONFERENCE PROCEEDINGS | 2001年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents an approach to increase the functional density of programmable logic devices (PLDs) using a programming technique called run-time reconfiguration (RTR) and the sequencing of time exclusive PLD configurations. The fundamental requirement permitting a design to increase the effective junctional density of a PLD using RTR is the ability to decompose the design functionally into time exclusive stages, where each stage is synthesized as a separate PLD configuration. These distinct PLD configurations are then sequenced optimally through the device during the run time. The distinctive feature of this approach is an increase in the effective functional density of a PLD as compared to a single-configured implementation since the effective junctional density in such an R TR system is proportional to the sum of all distinct PLD configurations.

引用

页码：1259 / 1264

页数：4

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