Tunnel DCIV extraction of dopant-impurity concentration, oxide thickness, and length, in the channel and extension regions of ultrathin gate-oxide MOS transistors

A methodology is described for extracting, between the source and drain, the spatial variations of surface dopant-impurity concentration and oxide thickness in the channel, drain/extension and source/extension regions using experimental tunnel direct current current-voltage data of the drain, source, and basewell terminal currents versus the gate/base voltage. An example is given using an pMOS transistor with W/L = 10 mu m/0.3 mu m fabricated by a factory 100-nm technology. Zeroth (constant values) and first-order (linear variation with position) representation formulas are used for the impurity concentration and oxide thickness to fit the experimental data, which also give the electrical lengths of the three regions.