A 550μW 10b 40MS/s SAR ADC with Multistep Addition-only Digital Error Correction

被引：0
|
作者：
Cho, Sang-Hyun [1 ]
Lee, Chang-Kyo [1 ]
Kwon, Jong-Kee [2 ]
Ryu, Seung-Tak [1 ]
机构：
[1] Korea Adv Inst Sci & Technol, Taejon 305701, South Korea
[2] ETRI, Taejon, South Korea
来源：
IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010 | 2010年
关键词：
SAR ADC; digital error correction;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A speed-enhanced 10b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented in this paper. Three virtually divided sub-DACs have a 0.5 LSB over-range between stages owing to additional decision phases incorporating DAC rearrange only. These redundancies make it possible to guarantee 10b linearity with a 37% speed enhancement under a 4b-accurate DAC settling condition at MSB decision. A prototype ADC was implemented in CMOS 0.13 mu m technology. The chip consumes 550 mu W and achieves a 50.6dB SNDR at 40MS/s under a 1.2V supply. The figure-of-merit (FOM) is 42fJ/conv-step.
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页数：4
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