Multimedia tool for self-learning VHDL

We have designed this tool in order to make easier the study, learning and application of VHDL to our Microelectronic Design university students, both undergraduate and postgraduate. First of all, we expose the syntax and all the elements language with plenty of examples and exercises to interactively try to resolve and evaluate their self-progress. This is addressed both to VHDL beginners and to those ones with basic knowledge. Then we explain the kernel of a VHDL simulator, so they can understand the main differences between hardware description languages and general purpose high level programming languages (C++, TurboPascal, etc.) and how digital systems are to be modelled in order to take into account its inherent concurrency. Finally we exposed a wide group of conventional MSI / LSI digital blocks, adequately selected and modelled in several ways, to allow them easily learning all of 1076.1 IEEE Standard possibilities to get digital systems be modelled and simulated satisfactorily.