A 75-GHz phase-locked loop in 90-nm CMOS technology

被引：73

作者：

Lee, Jri ^{[1
]}

Liu, Mingchung ^{[1
]}

Wang, Huaide ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2008年 / 43卷 / 06期

关键词：

frequency divider; phase and frequency detector (PFD); phase-locked loop (PLL); reference spurs; transmission line; voltage-controlled oscillator (VCO);

D O I：

10.1109/JSSC.2008.922719

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength oscillator to achieve high-frequency operation and a novel phase-frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an operation range of 320 MHz and reference sidebands of less than -72 dBc while consuming 88 mW from a 1.45-V supply.

引用

页码：1414 / 1426

页数：13

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