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- [2] Power-aware modulo scheduling for high-performance VLIW processors ISLPED'01: PROCEEDINGS OF THE 2001 INTERNATIONAL SYMPOSIUM ON LOWPOWER ELECTRONICS AND DESIGN, 2001, : 40 - 45
- [3] Power-balanced VLIW instruction scheduling using rough programming PROCEEDINGS OF THE FOURTH INTERNATIONAL CONFERENCE ON INFORMATION AND MANAGEMENT SCIENCES, 2005, 4 : 491 - 497
- [4] Power-aware instruction scheduling EMBEDDED AND UBIQUITOUS COMPUTING, PROCEEDINGS, 2006, 4096 : 35 - 44
- [5] Hierarchical instruction encoding for VLIW digital signal processors 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 3503 - 3506
- [6] VLIW instruction scheduling for DSP processors based on rough set theory ISSPA 2005: THE 8TH INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND ITS APPLICATIONS, VOLS 1 AND 2, PROCEEDINGS, 2005, : 311 - 314
- [7] A rough set approach to instruction-level power analysis of embedded VLIW processors PROCEEDINGS OF THE FOURTH INTERNATIONAL CONFERENCE ON INFORMATION AND MANAGEMENT SCIENCES, 2005, 4 : 479 - 483
- [9] Power Estimation Methodology for VLIW Digital Signal Processors 2008 42ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1-4, 2008, : 1840 - +
- [10] Power-aware scheduling for parallel security processors with analytical models LANGUAGES AND COMPILERS FOR HIGH PERFORMANCE COMPUTING, 2005, 3602 : 470 - 484