FinFET SRAM Process Technology for hp32 nm node and beyond

被引：0

作者：

Yagishita, Atsushi ^{[1
]}

机构：

[1] Toshiba Corp Semicond Co, Proc & Mfg Engn Ctr, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

2007 IEEE International Conference on Integrated Circuit Design and Technology, Proceedings | 2007年

关键词：

FinFET; SRAM; epi; Schottky; deviation;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Progresses in FinFET SRAM process technology are reviewed. The process technologies discussed in this paper are narrow and uniform fin formation, reduction of source/drain parasitic resistance, gate stack for threshold voltage control, integration scheme to build FinFET and planar FET on a wafer, and fin height tuning technique for beta-ratio control. These technologies are considered to enable the FinFET to become a prospective device for future SoC applications. Furthermore, FinFET future prospects are also presented.

引用

页码：59 / 62

页数：4