Advances in Wearable Brain-Computer Interfaces From an Algorithm-Hardware Co-Design Perspective

被引:7
作者
Byun, Wooseok [1 ]
Je, Minkyu [2 ]
Kim, Ji-Hoon [3 ]
机构
[1] SAPEON Korea, Architecture Team, Seongnam 13486, South Korea
[2] Korea Adv Inst Sci & Technol, Sch Elect Engn, Daejeon 34141, South Korea
[3] Ewha Womans Univ, Dept Elect & Elect Engn, Smart Factory Multidisciplinary Program, Seoul 03760, South Korea
关键词
Signal processing algorithms; Partitioning algorithms; Hardware; Wearable computers; Recording; Visualization; Signal processing; Brain-computer interface (BCI); algorithm-hardware co-design; domain-specific architecture; deep learning accelerator; linear algebra accelerator; DEEP NEURAL-NETWORK; ENHANCING DETECTION; PROCESSOR; CLASSIFICATION; IMPLEMENTATION; EEGNET; POWER;
D O I
10.1109/TCSII.2022.3177616
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Brain-computer interface (BCI), a communication technology between brain and computer developed for a long time since the 1970s, can be incorporated into wearable devices by developing powerful signal processing algorithms and semiconductor technologies. For a satisfactory user experience based on BCI, high information transfer rate and low power consumption should be considered together without losing accuracy. Although many existing BCI algorithms have been mainly focused solely on the accuracy, their deployment on wearable devices is not straightforward due to the limited hardware resources and computational capabilities. This tutorial summarizes recent advances in wearable BCI algorithms and hardware implementations from an algorithm-hardware co-design perspective and discusses future directions.
引用
收藏
页码:3071 / 3077
页数:7
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