Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

被引：4

作者：

Antonio Clemente, Juan ^{[1
]}

Franco, Francisco J. ^{[2
]}

Villa, Francesca ^{[6
,7
]}

Baylac, Maud ^{[6
,7
]}

Ramos, Pablo ^{[3
,4
,5
]}

Vargas, Vanessa ^{[3
,4
,5
]}

Mecha, Hortensia ^{[1
]}

Agapito, Juan A. ^{[2
]}

Velazco, Raoul ^{[3
,4
]}

机构：

[1] Univ Complutense Madrid, Fac Informat, Comp Architecture Dept, E-28040 Madrid, Spain

[2] Univ Complutense Madrid, Fac Ciencias Fis, Dept Fis Aplicada 3, E-28040 Madrid, Spain

[3] Univ Grenoble Alpes, F-38042 Grenoble, France

[4] CNRS, TIMA, F-38042 Grenoble, France

[5] Univ Fuerzas Armadas, ESPE, DEEE, Sangolqui, Ecuador

[6] Univ Grenoble Alpes, LPSC, F-38042 Grenoble, France

[7] CNRS, IN2P3, F-38042 Grenoble, France

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2016年 / 63卷 / 04期

关键词：

COTS; LPSRAM; neutron tests; radiation hardness; reliability; soft error; SRAM; COMMERCIAL SRAMS; IRRADIATION; UPSETS;

D O I：

10.1109/TNS.2016.2522819

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.

引用

页码：2072 / 2079

页数：8

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