Design, development and implementation of a low power and high speed pipeline A/D converter in submicron CMOS technology

This research paper focuses on the design, development and implementation of a pipelined analog to digital (A/D) converter of 8 bits with sampling rate of 25 MHz in 350 nm CMOS process technology. The architecture utilizes the digital correction for each stage based on a 1.5 bit per stage structure. A differential switched capacitor circuit consisting of a cascade gm-C op-amp with 200 MHz ft is used for sampling and amplification in each stage. Differential dynamic comparators are used to implement the decision levels required for the 1.5 bit per stage structure. Correction of the pipeline is accomplished by using digital correction circuit consist of D-latches and full adders. Finally, the paper describes the floorplan and layout of design.