Demonstration of a Novel Two Source Region Tunnel FET

被引：54

作者：

Bagga, Navjeet ^{[1
]}

Kumar, Anil ^{[1
]}

Dasgupta, Sudeb ^{[1
]}

机构：

[1] IIT Roorkee, Dept Elect & Commun Engn, Microelect & VLSI Grp, Roorkee 247667, Uttar Pradesh, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2017年 / 64卷 / 12期

关键词：

Band-to-band tunneling (BTBT); isolator oxide (IO); silicon-on-insulator (SOI); subthreshold slope (SS); tunnel FET (TFET); FIELD-EFFECT TRANSISTORS; ANALYTICAL-MODEL; GATE; PERFORMANCE; TFET;

D O I：

10.1109/TED.2017.2759898

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel silicon-on-insulator (SOI)-based tunnel FET (TFET) with two source regions (TSRs) is proposed and investigated by Sentaurus simulation. The incorporation of the TSR in the SOI platform augmented the effective tunneling area between source-channel junctions and hence boosts the drive current of the device. To restrain the leakage current at a lower value, we have introduced an isolator oxide which avoids the direct coupling of the source and the drain. The typical figure of merit of any device is its I-ON/I-OFF ratio, which is similar to 9 x 10(10) of our proposed structure. The impact of various device geometry variations has been studied and optimized accordingly through extensive simulation. We have also benchmarked our proposed TSR-TFET results with the modified L-shaped TFET, line tunneling-basedTFET, and point tunneling-based TFET and procured better results over all the reference devices.

引用

页码：5256 / 5262

页数：7

共 31 条

[21] Design Guideline of Si-Based L-Shaped Tunneling Field-Effect Transistors [J].