Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis

被引：73

作者：

Garg, Shelly ^{[1
]}

Saurabh, Sneh ^{[1
]}

机构：

[1] Indraprastha Inst Informat Technol, Dept ECE, Delhi, India

来源：

SUPERLATTICES AND MICROSTRUCTURES | 2018年 / 113卷

关键词：

TFET; Drain pocket; Ambipolar current; Tunneling barrier width; BTBT; FIELD-EFFECT TRANSISTORS; N-I-N; PERFORMANCE; VOLTAGE; TFETS; IMPROVEMENT; MOSFETS;

D O I：

10.1016/j.spmi.2017.11.002

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

In this paper, we investigate the impact of a drain-pocket (DP) adjacent to the drain region in Tunnel Field-Effect Transistors (TFETs) to effectively suppress the ambipolar current. Using calibrated two-dimensional device simulation, we examine the impact of DP in Double Gate TFET (DGTFET). We demonstrate the superiority of the DP technique over the existing techniques in controlling the ambipolar current. In particular, the addition of DP to a TFET is able to fully suppress the ambipolar current even when TFET is biased at high negative gate voltages and drain doping is kept as high as the source doping. Moreover, adding DP is complementary to the well-known technique of employ-ing source-pocket (SP) in a TFET since both need similar doping type and doping concentration. (C) 2017 Elsevier Ltd. All rights reserved.

引用

页码：261 / 270

页数：10

共 47 条

[21] Vertical Tunnel FET: Design Optimization With Triple Metal-Gate Layers [J].

Ko, Eunah ;

Lee, Hyunjae ;

Park, Jung-Dong ;

Shin, Changhwan .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (12) :5030-5035

[22] 2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure [J].

Kumar, Sanjay ;

Goel, Ekta ;

Singh, Kunal ;

Singh, Balraj ;

Singh, Prince Kumar ;

Baral, Kamalaksha ;

Jit, Satyabrata .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (03) :960-968

[23] A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO2/High-k Stacked Gate-Oxide Structure [J].

Kumar, Sanjay ;

Goel, Ekta ;

Singh, Kunal ;

Singh, Balraj ;

Kumar, Mirgender ;

Jit, Satyabrata .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (08) :3291-3299

[24] Random Variation Analysis and Variation-Aware Design of Symmetric Tunnel Field-Effect Transistor [J].

Lee, Hyunjae ;

Park, Seulki ;

Lee, Youngtaek ;

Nam, Hyohyun ;

Shin, Changhwan .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (06) :1778-1783

[25] Two-Dimensional Heterojunction Interlayer Tunneling Field Effect Transistors (Thin-TFETs) [J].

Li, Mingda ;

Esseni, David ;

Nahas, Joseph J. ;

Jena, Debdeep ;

Xing, Huili Grace .

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2015, 3 (03) :206-213

[26]

lonescu A. M., 2011, NATURE, V479

[27] Tunnel Field-Effect Transistors: State-of-the-Art [J].

Lu, Hao ;

Seabaugh, Alan .

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2014, 2 (04) :44-49

[28]

Luisier M., 2009, P IEEE INT EL DEV M, P1, DOI DOI 10.1109/IEDM.2009.5424280

[29] On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors [J].

Mookerjea, Saurabh ;

Krishnan, Ramakrishnan ;

Datta, Suman ;

Narayanan, Vijaykrishnan .

IEEE ELECTRON DEVICE LETTERS, 2009, 30 (10) :1102-1104

[30] Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics [J].

Morris, Daniel H. ;

Avci, Uygar E. ;

Rios, Rafael ;

Young, Ian A. .

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2014, 4 (04) :380-388

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