Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis

被引：73

作者：

Garg, Shelly ^{[1
]}

Saurabh, Sneh ^{[1
]}

机构：

[1] Indraprastha Inst Informat Technol, Dept ECE, Delhi, India

来源：

SUPERLATTICES AND MICROSTRUCTURES | 2018年 / 113卷

关键词：

TFET; Drain pocket; Ambipolar current; Tunneling barrier width; BTBT; FIELD-EFFECT TRANSISTORS; N-I-N; PERFORMANCE; VOLTAGE; TFETS; IMPROVEMENT; MOSFETS;

D O I：

10.1016/j.spmi.2017.11.002

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

In this paper, we investigate the impact of a drain-pocket (DP) adjacent to the drain region in Tunnel Field-Effect Transistors (TFETs) to effectively suppress the ambipolar current. Using calibrated two-dimensional device simulation, we examine the impact of DP in Double Gate TFET (DGTFET). We demonstrate the superiority of the DP technique over the existing techniques in controlling the ambipolar current. In particular, the addition of DP to a TFET is able to fully suppress the ambipolar current even when TFET is biased at high negative gate voltages and drain doping is kept as high as the source doping. Moreover, adding DP is complementary to the well-known technique of employ-ing source-pocket (SP) in a TFET since both need similar doping type and doping concentration. (C) 2017 Elsevier Ltd. All rights reserved.

引用

页码：261 / 270

页数：10

共 47 条

[11] Device and Architecture Outlook for Beyond CMOS Switches [J].

Bernstein, Kerry ;

Cavin, Ralph K., III ;

Porod, Wolfgang ;

Seabaugh, Alan ;

Welser, Jeff .

PROCEEDINGS OF THE IEEE, 2010, 98 (12) :2169-2184

[12] Silicon nanowire tunneling field-effect transistors [J].

Bjoerk, M. T. ;

Knoch, J. ;

Schmid, H. ;

Riel, H. ;

Riess, W. .

APPLIED PHYSICS LETTERS, 2008, 92 (19)

[13] Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric [J].

Boucart, Kathy ;

Ionescu, Adrian Mihai .

SOLID-STATE ELECTRONICS, 2007, 51 (11-12) :1500-1507

[14] Double-gate tunnel FET with high-κ gate dielectric [J].

Boucart, Kathy ;

Mihai Ionescu, Adrian .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) :1725-1733

[15] Improvement in Reliability of Tunneling Field-Effect Transistor With p-n-i-n Structure [J].

Cao, Wei ;

Yao, C. J. ;

Jiao, G. F. ;

Huang, Daming ;

Yu, H. Y. ;

Li, Ming-Fu .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (07) :2122-2126

[16] Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec [J].

Choi, Woo Young ;

Park, Byung-Gook ;

Lee, Jong Duk ;

Liu, Tsu-Jae King .

IEEE ELECTRON DEVICE LETTERS, 2007, 28 (08) :743-745

[17] Impact of Super-Linear Onset, Off-Region Due to Uni-Directional Conductance and Dominant CGD on Performance of TFET-Based Circuits [J].

Dagtekin, Nilay ;

Ionescu, Adrian Mihai .

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2015, 3 (03) :239-245

[18] CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With ≤ 50-mV/decade Subthreshold Swing [J].

Gandhi, Ramanathan ;

Chen, Zhixian ;

Singh, Navab ;

Banerjee, Kaustav ;

Lee, Sungjoo .

IEEE ELECTRON DEVICE LETTERS, 2011, 32 (11) :1504-1506

[19] Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor [J].

Jhaveri, Ritesh ;

Nagavarapu, Venkatagirish ;

Woo, Jason C. S. .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (01) :80-86

[20] Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits [J].

Khatami, Yasin ;

Banerjee, Kaustav .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (11) :2752-2761

← 1 2 3 4 5 →