Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit

被引:41
作者
Kilchytska, V. [1 ]
Arshad, M. K. Md [1 ,2 ]
Makovejev, S. [3 ]
Olsen, S. [3 ]
Andrieu, F. [4 ]
Poiroux, T. [4 ]
Faynot, O. [4 ]
Raskin, J. -P. [1 ]
Flandre, D. [1 ]
机构
[1] Catholic Univ Louvain, ICTEAM Inst, Louvain, Belgium
[2] Univ Malaysia Perlis, Sch Microelect Engn, Kangar, Malaysia
[3] Newcastle Univ, Sch Elect Elect & Comp Engn, Newcastle Upon Tyne, Tyne & Wear, England
[4] CEA Leti, F-38054 Grenoble 9, France
关键词
Ultra-thin body FD SOI MOSFETs; Ultra-thin BOX; Analog figures of merit; Cut-off frequency; High-temperature; Output conductance; SIGNAL OUTPUT CONDUCTANCE; ON-NOTHING SON; SUBTHRESHOLD SLOPE; THRESHOLD VOLTAGE; MOSFETS; GATE; PERFORMANCE; BEHAVIOR; DEVICES; FINFETS;
D O I
10.1016/j.sse.2011.11.020
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we analyze, for the first time to our best knowledge, the perspectives of ultra-thin body and ultra-thin BOX (UTBB) SOI CMOS technology for analog applications. We show that UTBB is a promising contender for analog applications, exhibiting high maximum transconductance, drive current, intrinsic gain and achievable cut-off frequencies in the range of 150-220 GHz. Effect of operation regime, substrate bias, channel width and high temperature (up to 250 degrees C) on analog figures-of-merit (FoM) are analyzed. Benchmarking of UTBB with other technologies (as planar FD SOI, different FinFETs, UTB with thick BOX) is presented. (C) 2011 Elsevier Ltd. All rights reserved.
引用
收藏
页码:50 / 58
页数:9
相关论文
共 56 条
[1]   High-temperature performance of state-of-the-art triple-gate transistors [J].
Akarvardar, K. ;
Mercha, A. ;
Simoen, E. ;
Subramanian, V. ;
Claeys, C. ;
Gentil, P. ;
CristoloveanU, S. .
MICROELECTRONICS RELIABILITY, 2007, 47 (12) :2065-2069
[2]   Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20nm Low Power CMOS and Beyond [J].
Andrieu, F. ;
Weber, O. ;
Mazurier, J. ;
Thomas, O. ;
Noel, J-P. ;
Fenouillet-Beranger, C. ;
Mazellier, J-P ;
Perreau, P. ;
Poiroux, T. ;
Morand, Y. ;
Morel, T. ;
Allegret, S. ;
Loup, V. ;
Barnola, S. ;
Martin, F. ;
Damlencourt, J-F ;
Servin, I. ;
Casse, M. ;
Garros, X. ;
Rozeau, O. ;
Jaud, M-A. ;
Cibrario, G. ;
Cluzel, J. ;
Toffoli, A. ;
Allain, F. ;
Kies, R. ;
Lafond, D. ;
Delaye, V. ;
Tabone, C. ;
Tosti, L. ;
Brevard, L. ;
Gaud, P. ;
Paruchuri, V. ;
Bourdelle, K. K. ;
Schwarzenbach, W. ;
Bonnin, O. ;
Nguyen, B-Y ;
Doris, B. ;
Boeuf, F. ;
Skotnicki, T. ;
Faynot, O. .
2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, :57-+
[3]  
[Anonymous], IEEE INT EL DEV M IE
[4]   DC and low frequency noise characterization of FinFET devices [J].
Bennamane, K. ;
Boutchacha, T. ;
Ghibaudo, G. ;
Mouis, M. ;
Collaert, N. .
SOLID-STATE ELECTRONICS, 2009, 53 (12) :1263-1267
[5]   Integration of buried insulators with high thermal conductivity in SOI MOSFETs:: Thermal properties and short channel effects [J].
Bresson, N ;
Cristoloveanu, S ;
Mazuré, C ;
Letertre, F ;
Iwai, H .
SOLID-STATE ELECTRONICS, 2005, 49 (09) :1522-1528
[6]  
Burignat S., 2009, Proceedings of the 39th European Solid-State Device Research Conference. ESSDERC 2009, P141, DOI 10.1109/ESSDERC.2009.5331323
[7]   Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel [J].
Burignat, S. ;
Flandre, D. ;
Arshad, M. K. Md ;
Kilchytska, V. ;
Andrieu, F. ;
Faynot, O. ;
Raskin, J. -P. .
SOLID-STATE ELECTRONICS, 2010, 54 (02) :213-219
[8]  
Colinge J.P., 1997, Silicon-On-Insulator Technology: Materials to VLSI
[9]   A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node [J].
Collaert, N ;
Dixit, A ;
Goodwin, M ;
Anil, KG ;
Rooyackers, R ;
Degroote, B ;
Leunissen, LHA ;
Veloso, A ;
Jonckheere, R ;
De Meyer, K ;
Jurczak, M ;
Biesemans, S .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (08) :568-570
[10]  
Collaert N., 2008, ICICDT, P59