Energy recovery design for low-power ASICs

Three decades ago, theoretical physicists suggested that the controlled recovery of charges could result in electronic circuitry whose power dissipation approaches thermodynamic limits, growing at a significantly slower pace than the fCV(2) rate for CMOS switching power. Early engineering research in this field, which became generally known as adiabatic computing, focused on the asymptotic energetics of computation, exploring VLSI designs that use reversible logic and adiabatic switching to preserve information and achieve nearly zero power dissipation as operating frequencies approach zero. Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at substantially lower power dissipation levels than their conventional counterparts. Although their origins can be traced back to the early adiabatic circuits, these so-called energy-recovering systems approach charge recycling from a more practical angle, achieving operating frequencies in the hundreds of MHz with relatively low overhead. Among other energy recovering designs, researchers in the field have demonstrated micro-controllers, standard-cell ASICs, SRAMs, LCD panel drivers, I/O drivers, and multi-GHz clock networks. In this tutorial, we will present an overview of the field, focusing on the most promising charge recovering design techniques for ASICs that are close to integration into the field.