Porous dielectric Dual Damascene Patterning issues for 65nm node : Can architecture bring a solution?

被引：19

作者：

Assous, M ^{[1
]}

Simon, J ^{[1
]}

Broussous, L ^{[1
]}

Bourlot, C ^{[1
]}

Fayolle, M ^{[1
]}

Louveau, O ^{[1
]}

Roman, A ^{[1
]}

Tabouret, E ^{[1
]}

Feldis, H ^{[1
]}

Louis, D ^{[1
]}

Torres, J ^{[1
]}

机构：

[1] CEA Grenoble, LETI, F-38054 Grenoble 9, France

来源：

PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2003年

关键词：

D O I：

10.1109/IITC.2003.1219723

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A dual hard mask, dual damascene architecture was developed to circumvent integration problems brought by porous ULK dielectric use. It was demonstrated that a via first strategy with adequately defined hard masks can improve patterning conditions.

引用

页码：97 / 99

页数：3