High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology

被引：0

作者：

Sung, Gaeryun ^{[1
]}

Han, Jaeduk ^{[1
]}

机构：

[1] Hanyang Univ, Dept Elect Engn, Seoul, South Korea

来源：

18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021) | 2021年

基金：

新加坡国家研究基金会;

关键词：

StorngARM latch; phase detector; clock-to-Q delay; power consumption;

D O I：

10.1109/ISOCC53507.2021.9613931

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a high-speed strongARM-latch-based bang-bang phase detector (PD). Instead of using D-flipflops (DFF) or D-latches, which are used in conventional bang-bang PDs, strongARM latches are used to achieve high sensitivity owing to their regeneration behaviors. By comparing the clock-to-Q delay(tcq) and maximum data rate of conventional and proposed phase detectors, it is found that the proposed strongARM-latch-based bang-bang PD has a smaller clock-to-Q delay and a higher data rate.

引用

页码：377 / 378

页数：2

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