A 4-bit 9 KS/s Distortionless Successive Approximation ADC in 180-nm CMOS Technology

被引：0

作者：

Dipu, P. ^{[1
]}

Saidulu, B. ^{[1
]}

Aravind, K. ^{[1
]}

Raj, Johny S. ^{[1
]}

Sivasankaran, K. ^{[1
]}

机构：

[1] VIT Univ, Sch Elect Engn SENSE, Vellore, Tamil Nadu, India

来源：

ARTIFICIAL INTELLIGENCE AND EVOLUTIONARY ALGORITHMS IN ENGINEERING SYSTEMS, VOL 1 | 2015年 / 324卷

关键词：

D O I：

10.1007/978-81-322-2126-5_7

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In recent years, analog-to-digital converters are the crucial part of many applications. In this paper, we proposed a 1.8 V capacitor-array-based successive approximation ADC. This SAR ADC uses bootstrapped switch to decrease distortion, and comparison is done using a pre-amplifier preceding a latched comparator. A 4-bit SAR ADC with high resolution was designed in 180-nm CMOS process. This paper aims at describing the design of a discrete-component, successive approximation register analog-to-digital converter (SAR ADC). The performance evaluation was done using Cadence ADE tool.

引用

页码：55 / 63

页数：9

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